This invention relates generally to semiconductors having defect denuded zones (DZs) and more particularly to electronic devices formed in such semiconductors having topography-aligned defect denuded zones.
As is known in the art, Czochralski-grown (CZ) silicon substrates are used today in making semiconductor devices. These CZ-grown silicon substrates typically contain 25-35 parts per million atomic (ppma) of oxygen, virtually all of which is interstitial, i.e., between silicon lattice sites. This oxygen content, which is introduced into the semiconductor material in a process-related manner by the use of quartz workpieces (for example, the crucibles used for Czochralski crystal pulling) is thoroughly desirable because it presents lattice defect nucleation centers for impurities in the crystal lattice. These nucleation centers provide a purification effect, known as "internal gettering", as a result of concentrating the residual impurities. However, this oxygen content is only useful in the interior of the semiconductor wafer. In the surface region of the wafer, i.e., the region where electronic devices are formed, these oxygen centers cause considerable disturbances. More particularly, as a consequence of the processing steps used to form the devices, e.g., epitaxy, dopant treatment, oxidation, and the heat-treatment steps associated therewith, the oxygen centers have a tendency to precipitate formation and consequently cause stresses in the lattice which result, in turn, in the failure of the electronic devices. It is desirable, therefore, to use wafers which contain oxygen-depleted surface zones (i.e., defect denuded zones) which are several .mu.m thick. Processes for producing a denuded zone (DZ) have been known for a long time. For example, oxygen can be caused to diffuse out of the surface by heat-treating (e.g. annealing) silicon wafers in a furnace (at temperatures, for example, of 1000.degree. C. to 1200.degree. C.) under an inert gas atmosphere. After a time of about five hours at a temperature of 1000.degree. C., the layer thickness of the denuded zone achievable solely by diffusing out oxygen is more than 10 .mu.m (Huber, D; Reffle, J.: Solid State Techn. 26(8), 1983, pages 183). Other methods to produce defect denuded zones including using epitaxial grown layers. In both cases, (i.e., thermal anneal and an epitaxial grown layers), the DZ is basically parallel to the surface of the silicon wafer. Adjacent to the DZ is the defective, oxygen containing, zone having the internal gettering sites produced by the oxygen. The DZ must be sufficiently deep such that the electronic device to be formed later does not extend into the defective zone. On the other hand, the DZ should be as shallow as possible such that the internal gettering sites are close enough to the electronic device in order to provide sufficient gettering efficiency for crystal defects, such as oxygen precipitates, dislocations, stacking faults and contaminants, such as metals like Fe, CU, Ni, Cr, etc., which may be in the device region.
As is also known in the art, one type of electronic device which is formed in the semiconductor is a dynamic random access memory (DRAM). One type of DRAM uses trench capacitors to store charge. A trench capacitor is formed vertically into the surface of the silicon wafer to decrease device surface dimension and thereby increasing integration density as compared to a stack capacitor. A typical trench capacitor can be up to 7-8 .mu.m deep. In order to avoid degeneration of device performance, or complete device failure, the whole area near the wafer surface containing both transistors and trench capacitors must be kept virtually free of the aforementioned crystal defects.
As is also known in the art, with current technology used to form DZs essentially parallel to the wafer surface, the rate of oxygen precipitation is not completely uniform across the wafer. The local DZ depths for different sites on one wafer, as well as from wafer-to-wafer, are statistically distributed. More particularly, the initial oxygen concentration is typically higher near the edges of the wafer than near the center of the wafer. If, for example, the DZ depth is chosen as 10 .mu.m to accommodate an 8 .mu.m trench capacitor, at some positions on the wafer, especially near the wafer edge, the DZ will, with high probability, be less than 8 .mu.m. This can either result in spikes during reactive ion etching (RIE) of the trench structure or in defect formation near the trench leading to a degradation of the node dielectric (i.e., the dielectric lining the walls of the trench and disposed between the doped polycrystalline silicon in the trench to form one electrode, or plate, for the capacitor, and the doped region in the silicon substrate separated by the dielectric lining the trench used to form the second electrode of the capacitor). If defects, such as oxygen precipitates and dislocation loops, are located too close to a charged trench capacitor, charge leakage can occur leading to significant degradation of retention time for charge in the DRAM cell trench capacitor.
Further, a relatively large thermal budget (i.e., high temperature and long anneal time) is required for formation of a DZ in a CZ wafer by a high temperature out-diffusion step according to current technology. For example, for a CZ wafer having an initial interstitial oxygen concentration of about 30 ppma, the forming of a DZ with a depth of about 10 .mu.m requires a heat treatment of about one hour at 1150.degree. C., while forming a DZ with a depth of about 20 .mu.m requires at least about four to five hours at 1150.degree. C. Still further, because interstitial oxygen concentration monotonously increases with depth from the surface, the number of oxygen micro-precipitates, which can also degrade device performance if located too closely to electronic devices such as transistors or capacitors, also increases with depth. In other words, the quality of the DZ decreases with increasing depth from the wafer surface.
The quality of the first few microns of the DZ is predominately a result of the surface condition during the thermal treatment for DZ formation. Annealing in hydrogen, or an inert atmosphere (at longer anneal times) can result in oxygen concentrations at the wafer surface below 1 ppma. A typical process used is to perform an anneal in pure hydrogen for one hour at 1200.degree. C. resulting in a DZ depth of about 20 .mu.m; however, the cost of this process can be relatively high. One method of forming a high quality DZ irrespective of the depth from the surface is growing an epitaxial silicon layer on the DZ silicon surface, such as a p.sup.- -type conductivity epitaxial layer on a p-type silicon substrate, or an n.sup.- -type epitaxial layer on an n-type silicon substrate. In the epitaxial layer, the total concentration of oxygen will be typically below 2 ppma compared to typically 30 ppma in non-annealed CZ silicon substrates. Because of the high cost of manufacturing wafers with epitaxial layers with more than 2-3 .mu.m thickness, such wafers are rarely used in device production. The additional cost for producing epitaxial layered wafers for thickness as small as 2-3 .mu.m is still relatively high compared to conventional CZ wafers. In this case, however, oxygen from CZ substrates will diffuse into the epitaxial layer during device manufacturing processes such that the quality of the DZ near the wafer surface will not be noticeably better than that of, for example, a hydrogen annealed wafer. Further, the thicker the epitaxial layer the further the gettering sites move away from the device active region. That is, it is desired that the getting sites in the epitaxial layer be just below the active region where the active devices are formed. The thicker the epitaxial layer, however, the further the gettering sites move away from the active region. Also, the thick epitaxial layer is more susceptible to dislocations propagation and this leads to reduced yield if the epitaxial layer is too thick.